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64 | #define ECB_PTRSIZE 4 |
64 | #define ECB_PTRSIZE 4 |
65 | #endif |
65 | #endif |
66 | #endif |
66 | #endif |
67 | |
67 | |
68 | /* work around x32 idiocy by defining proper macros */ |
68 | /* work around x32 idiocy by defining proper macros */ |
69 | #if __x86_64 || _M_AMD64 |
69 | #if __amd64 || __x86_64 || _M_AMD64 || _M_X64 |
70 | #if _ILP32 |
70 | #if _ILP32 |
71 | #define ECB_AMD64_X32 1 |
71 | #define ECB_AMD64_X32 1 |
72 | #else |
72 | #else |
73 | #define ECB_AMD64 1 |
73 | #define ECB_AMD64 1 |
74 | #endif |
74 | #endif |
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134 | || defined __ARM_ARCH_6K__ || defined __ARM_ARCH_6ZK__ |
134 | || defined __ARM_ARCH_6K__ || defined __ARM_ARCH_6ZK__ |
135 | #define ECB_MEMORY_FENCE __asm__ __volatile__ ("mcr p15,0,%0,c7,c10,5" : : "r" (0) : "memory") |
135 | #define ECB_MEMORY_FENCE __asm__ __volatile__ ("mcr p15,0,%0,c7,c10,5" : : "r" (0) : "memory") |
136 | #elif defined __ARM_ARCH_7__ || defined __ARM_ARCH_7A__ \ |
136 | #elif defined __ARM_ARCH_7__ || defined __ARM_ARCH_7A__ \ |
137 | || defined __ARM_ARCH_7M__ || defined __ARM_ARCH_7R__ |
137 | || defined __ARM_ARCH_7M__ || defined __ARM_ARCH_7R__ |
138 | #define ECB_MEMORY_FENCE __asm__ __volatile__ ("dmb" : : : "memory") |
138 | #define ECB_MEMORY_FENCE __asm__ __volatile__ ("dmb" : : : "memory") |
139 | #elif __sparc || __sparc__ |
139 | #elif (__sparc || __sparc__) && !__sparcv8 |
140 | #define ECB_MEMORY_FENCE __asm__ __volatile__ ("membar #LoadStore | #LoadLoad | #StoreStore | #StoreLoad" : : : "memory") |
140 | #define ECB_MEMORY_FENCE __asm__ __volatile__ ("membar #LoadStore | #LoadLoad | #StoreStore | #StoreLoad" : : : "memory") |
141 | #define ECB_MEMORY_FENCE_ACQUIRE __asm__ __volatile__ ("membar #LoadStore | #LoadLoad" : : : "memory") |
141 | #define ECB_MEMORY_FENCE_ACQUIRE __asm__ __volatile__ ("membar #LoadStore | #LoadLoad" : : : "memory") |
142 | #define ECB_MEMORY_FENCE_RELEASE __asm__ __volatile__ ("membar #LoadStore | #StoreStore") |
142 | #define ECB_MEMORY_FENCE_RELEASE __asm__ __volatile__ ("membar #LoadStore | #StoreStore") |
143 | #elif defined __s390__ || defined __s390x__ |
143 | #elif defined __s390__ || defined __s390x__ |
144 | #define ECB_MEMORY_FENCE __asm__ __volatile__ ("bcr 15,0" : : : "memory") |
144 | #define ECB_MEMORY_FENCE __asm__ __volatile__ ("bcr 15,0" : : : "memory") |
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177 | * #define ECB_MEMORY_FENCE __c11_atomic_thread_fence (__ATOMIC_SEQ_CST) |
177 | * #define ECB_MEMORY_FENCE __c11_atomic_thread_fence (__ATOMIC_SEQ_CST) |
178 | */ |
178 | */ |
179 | |
179 | |
180 | #elif ECB_GCC_VERSION(4,4) || defined __INTEL_COMPILER || defined __clang__ |
180 | #elif ECB_GCC_VERSION(4,4) || defined __INTEL_COMPILER || defined __clang__ |
181 | #define ECB_MEMORY_FENCE __sync_synchronize () |
181 | #define ECB_MEMORY_FENCE __sync_synchronize () |
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182 | #elif _MSC_VER >= 1500 /* VC++ 2008 */ |
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183 | /* apparently, microsoft broke all the memory barrier stuff in Visual Studio 2008... */ |
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184 | #pragma intrinsic(_ReadBarrier,_WriteBarrier,_ReadWriteBarrier) |
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185 | #define ECB_MEMORY_FENCE _ReadWriteBarrier (); MemoryBarrier() |
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186 | #define ECB_MEMORY_FENCE_ACQUIRE _ReadWriteBarrier (); MemoryBarrier() /* according to msdn, _ReadBarrier is not a load fence */ |
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187 | #define ECB_MEMORY_FENCE_RELEASE _WriteBarrier (); MemoryBarrier() |
182 | #elif _MSC_VER >= 1400 /* VC++ 2005 */ |
188 | #elif _MSC_VER >= 1400 /* VC++ 2005 */ |
183 | #pragma intrinsic(_ReadBarrier,_WriteBarrier,_ReadWriteBarrier) |
189 | #pragma intrinsic(_ReadBarrier,_WriteBarrier,_ReadWriteBarrier) |
184 | #define ECB_MEMORY_FENCE _ReadWriteBarrier () |
190 | #define ECB_MEMORY_FENCE _ReadWriteBarrier () |
185 | #define ECB_MEMORY_FENCE_ACQUIRE _ReadWriteBarrier () /* according to msdn, _ReadBarrier is not a load fence */ |
191 | #define ECB_MEMORY_FENCE_ACQUIRE _ReadWriteBarrier () /* according to msdn, _ReadBarrier is not a load fence */ |
186 | #define ECB_MEMORY_FENCE_RELEASE _WriteBarrier () |
192 | #define ECB_MEMORY_FENCE_RELEASE _WriteBarrier () |