| 1 | |
1 | |
| 2 | - major size optimisations |
2 | - major size optimisations |
| 3 | - struct layout for both typical CISC and RISC cpus. |
3 | - struct layout for both typical CISC and RISC cpus. |
| 4 | - optional error messages. |
4 | - optional error messages. |
| 5 | - optional error checking. |
5 | - optional error checking. |
| 6 | - cell size reduced from 24 to 8 bytes on amd64 (at the cost |
6 | - cell size reduced by not storing both float and int forms of a number, |
| 7 | of speed and code size hit). |
|
|
| 8 | - major dependency optimisations (no stdio etc.) |
7 | - major dependency optimisations (no stdio etc.) |
| 9 | - faster and vastly simpler vector memory management (execution speed |
8 | - faster and vastly simpler vector memory management (execution speed |
| 10 | is roughly twice faster than tinyscheme when optimised for size, and 2.5 |
9 | is roughly twice faster than tinyscheme when optimised for size, and 2.5 |
| 11 | times faster when optimised for speed). |
10 | times faster when optimised for speed). |
| 12 | - no need for consecutive cells |
11 | - no need for consecutive cells |
