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Comparing vt102/vt102 (file contents):
Revision 1.16 by root, Wed Dec 3 02:15:18 2014 UTC vs.
Revision 1.19 by root, Wed Dec 3 02:40:34 2014 UTC

… …
27shift, ($VT102 = 0), ($AVO = 0) if $ARGV[0] =~ /^-?-vt100$/; 27shift, ($VT102 = 0), ($AVO = 0) if $ARGV[0] =~ /^-?-vt100$/;
28shift, ($VT102 = 0) if $ARGV[0] =~ /^-?-vt100\+avo$/; 28shift, ($VT102 = 0) if $ARGV[0] =~ /^-?-vt100\+avo$/;
29shift if $ARGV[0] =~ /^-?-vt102$/; 29shift if $ARGV[0] =~ /^-?-vt102$/;
30shift, ($VT131 = 1) if $ARGV[0] =~ /^-?-vt131$/; 30shift, ($VT131 = 1) if $ARGV[0] =~ /^-?-vt131$/;
31 31
32# vt100 wps = word processing roms
33# vt101 = vt102 - avo, but custom rom? really?
34# vt103 = vt100 + tu58 tape drive
35# vt125 = vt100 + gpo graphics processor
36# vt132 = vt100 + avo, stp
37# vt180 = vt100 + z80 cp/m
38
32if ($ARGV[0] =~ /^-/) { 39if ($ARGV[0] =~ /^-/) {
33 die <<EOF; 40 die <<EOF;
34 41
35VT102, A VT100/101/102/131 SIMULATOR 42VT102, A VT100/102/131 SIMULATOR
36 43
37Usage: 44Usage:
38 45
39 $0 [option] [program [args]] 46 $0 [option] [program [args]]
40 47
… …
104my ($PC, $SP, $IFF, $FA, $FZ, $FS, $FP, $FC); 111my ($PC, $SP, $IFF, $FA, $FZ, $FS, $FP, $FC);
105 112
106my $RST = 0; # 8080 pending interrupts 113my $RST = 0; # 8080 pending interrupts
107my $INTMASK = 7; # 8085 half interrupts 114my $INTMASK = 7; # 8085 half interrupts
108my $INTPEND = 0; # 8085 half interrupts 115my $INTPEND = 0; # 8085 half interrupts
109
110my $x; # dummy temp for instructions
111 116
112my $CLK; # rather inexact clock 117my $CLK; # rather inexact clock
113 118
114############################################################################# 119#############################################################################
115# the dreaded NVR1400 chip. not needed to get it going, but provided anyway 120# the dreaded NVR1400 chip. not needed to get it going, but provided anyway
… …
292sub in_1b { 0xff } # vt102 unknown 297sub in_1b { 0xff } # vt102 unknown
293 298
294############################################################################# 299#############################################################################
295# 8085 cpu opcodes and flag handling 300# 8085 cpu opcodes and flag handling
296 301
302my $x; # dummy scratchpad for opcodes
303
297sub sf { # set flags (ZSC - AP not implemented) 304sub sf { # set flags (ZSC - AP not implemented)
298 $FS = $_[0] & 0x080; 305 $FS = $_[0] & 0x080;
299 $FZ = !($_[0] & 0x0ff); 306 $FZ = !($_[0] & 0x0ff);
300 $FC = $_[0] & 0x100; 307 $FC = $_[0] & 0x100;
301 308
… …
399$op[0xb0 + $_] = 'sf8 $A |= ' . $reg[$_] for 0..7; # ora 406$op[0xb0 + $_] = 'sf8 $A |= ' . $reg[$_] for 0..7; # ora
400$op[0xb8 + $_] = 'sf $x = $A - ' . $reg[$_] for 0..7; # cmp 407$op[0xb8 + $_] = 'sf $x = $A - ' . $reg[$_] for 0..7; # cmp
401# possible todo: optimize ora a, maybe xra a 408# possible todo: optimize ora a, maybe xra a
402 409
403$op[0xc6] = 'sf $A += IMM8'; # adi 410$op[0xc6] = 'sf $A += IMM8'; # adi
404# ce ADI NYI 411# ce ACI NYI, apparently unused
405$op[0xd6] = 'sf $A -= IMM8'; # sui 412$op[0xd6] = 'sf $A -= IMM8'; # sui
406# de SBI NYI 413# de SBI NYI, apparently unused
407$op[0xe6] = 'sf8 $A &= IMM8'; # ani 414$op[0xe6] = 'sf8 $A &= IMM8'; # ani
408$op[0xee] = 'sf8 $A ^= IMM8'; # xri 415$op[0xee] = 'sf8 $A ^= IMM8'; # xri
409$op[0xf6] = 'sf8 $A |= IMM8'; # ori 416$op[0xf6] = 'sf8 $A |= IMM8'; # ori
410$op[0xfe] = 'sf $A - IMM8'; # cpi 417$op[0xfe] = 'sf $A - IMM8'; # cpi
411 418
… …
429$op[0xc9] = 'JMP POP + POP * 256'; # ret 436$op[0xc9] = 'JMP POP + POP * 256'; # ret
430 437
431$op[0xc7 + $_ * 8] = "JMP $_ * 8" for 0..7; # rst 438$op[0xc7 + $_ * 8] = "JMP $_ * 8" for 0..7; # rst
432 439
433$op[0xe9] = 'JMP $H * 256 + $L'; # pchl 440$op[0xe9] = 'JMP $H * 256 + $L'; # pchl
434# f9 SPHL NYI 441# f9 SPHL NYI, apparently unused
435 442
436$op[0x37] = '$FC = 1 '; # stc 443$op[0x37] = '$FC = 1 '; # stc
437$op[0x3f] = '$FC = !$FC'; # cmc 444$op[0x3f] = '$FC = !$FC'; # cmc
438 445
439$op[0xd3] = 'OUT'; # out 446$op[0xd3] = 'OUT'; # out
440$op[0xdb] = 'IN'; # in 447$op[0xdb] = 'IN'; # in
441 448
442$op[0xeb] = '($D, $E, $H, $L) = ($H, $L, $D, $E)'; # xchg 449$op[0xeb] = '($D, $E, $H, $L) = ($H, $L, $D, $E)'; # xchg
443 450
444# e3 xthl NYI # @ 917b, hl <-> (sp) 451# e3 xthl NYI # @ 917b in e69, hl <-> (sp)
445 452
446$op[0x20] = '$A = $INTPEND * 16 + $INTMASK + ($IFF && 8)'; # rim (incomplete) 453$op[0x20] = '$A = $INTPEND * 16 + $INTMASK + ($IFF && 8)'; # rim (incomplete)
447$op[0x30] = '$INTMASK = $A & 7 if $A & 8'; # sim (incomplete) 454$op[0x30] = '$INTMASK = $A & 7 if $A & 8'; # sim (incomplete)
448 455
449$op[0xf3] = '$IFF = 0'; # DI 456$op[0xf3] = '$IFF = 0'; # DI
… …
746 eval "use integer; sub { $insn }" or die "$insn: $@" 753 eval "use integer; sub { $insn }" or die "$insn: $@"
747 })->(); 754 })->();
748 755
749 ++$CLK; 756 ++$CLK;
750 757
751 # things we do from time too time only 758 # things we do from time to time only
752 unless ($CLK & 0xf) { 759 unless ($CLK & 0xf) {
753 # do I/O 760 # do I/O
754 761
755 unless ($CLK & 0xfff) { 762 unless ($CLK & 0xfff) {
756 763
… …
800 # 6.5 vt125 mb7 read ready (something modem?) 807 # 6.5 vt125 mb7 read ready (something modem?)
801 # 7.5 vt125 mb7 vblank h(?) 808 # 7.5 vt125 mb7 vblank h(?)
802 # trap vt125 mbi init h(?) 809 # trap vt125 mbi init h(?)
803 my $vec; 810 my $vec;
804 811
805 $x = $INTPEND & ~$INTMASK; 812 my $pend = $INTPEND & ~$INTMASK;
806 813
807 if ($x & 1) { $vec = 0x2c; $INTPEND &= ~1; 814 if ($pend & 1) { $vec = 0x2c; $INTPEND &= ~1;
808 } elsif ($x & 2) { $vec = 0x34; $INTPEND &= ~2; 815 } elsif ($pend & 2) { $vec = 0x34; $INTPEND &= ~2;
809 } elsif ($x & 4) { $vec = 0x3c; $INTPEND &= ~4; 816 } elsif ($pend & 4) { $vec = 0x3c; $INTPEND &= ~4;
810# } elsif ($RST ) { $vec = $RST * 8; $RST = 0; # the vt102 firmware doesn't like combined interrupts 817# } elsif ($RST ) { $vec = $RST * 8; $RST = 0; # the vt102 firmware doesn't like combined interrupts
811 } elsif ($RST & 1) { $vec = 0x08; $RST &= ~1; # separate is better for vt102 818 } elsif ($RST & 1) { $vec = 0x08; $RST &= ~1; # separate is better for vt102
812 } elsif ($RST & 2) { $vec = 0x10; $RST &= ~2; 819 } elsif ($RST & 2) { $vec = 0x10; $RST &= ~2;
813 } elsif ($RST & 4) { $vec = 0x20; $RST &= ~4; 820 } elsif ($RST & 4) { $vec = 0x20; $RST &= ~4;
814 } else { 821 } else {

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